- #MEMORY MASTER RAM DDR3 SOFTWARE#
- #MEMORY MASTER RAM DDR3 SERIES#
- #MEMORY MASTER RAM DDR3 FREE#
Memory voltage was set to either to 1.5 or 1.65 V. During all the test Command Rate was set to 1T, except for default settings - DDR3-1600 9-9-9-24. After stability test run the CPU enabled energy saving feature which resulted in CPU multiplier drop to x16. The processor operated at default settings - during test the clock raised from 3.3 to 3.7 GHz due to Turbo Boost technology.
#MEMORY MASTER RAM DDR3 SOFTWARE#
AIDA64 system information and diagnosis software suite (shareware)ĬPU basic clock (BCLK) has been set to 100 MHz. Storage drive: Western Digital WD10EADS-65L5B1. Graphics card: MSI N570GTX Twin Frozr II/OC. Processor: Intel Core i5–2500K, Stepping D2. Motherboard: ASUS P8P67, Intel P67, BIOS 1704. The PHY modules have tuneable delays, it would be good if these were automatically tuned at startup to simplify integration efforts (although this would increase LUT usage).For memory testing we used benchtable with the following configuration:. Add optional DDR scheduler logic on the frontend of the core to improve read/write thrashing performance (re-order and coalesce). Support for AXI-4 WRAP bursts - these are often used with cache controllers which do critical word first fetches. This works reliably on the board/clock speeds tested, but really could do with fixing! ECP5 PHY is sub-optimal - relies on aligning the read data capture to the internal clock instead of capturing on the DQS input. These boards have also booted Linux reliably with this DDR core, at the same time as been stressed by video frame buffer accesses to DDR. The performance and error checking was done using this RAM Tester. 
LambaConcept ECPIX-5 (Lattice ECP5 + MT41K256M16RE-125). Digilent Arty A7 (Xilinx Artix + MT41K128M16JT-125). Verified under simulation, then exercised on the following FPGA boards It should be noted that the same project using the Xilinx MIG DDR3 controller takes 33% of the FPGA LUTs (vs 9% with this core). On the Digilent Arty A7 running at 100MHz (max 400MBytes/s of bandwidth available), performing sequential reads / writes Īs for area, on the Xilinx Artix 7 (XC7A35T), the area used by the core (plus a small UART to AXI-4 bridge) Performance for sequential burst accesses is good, as a burst of the same type - read or write, will be pipelined to an already open row.Ĭurrently, there is no capability for read/write re-ordering/coalescing, so random read/write performance will not be optimal (this might be addressed in future releases). 
Standardized DFI interface between memory controller core and PHY. Support up to 8 open rows, allowing back-to-back read/write bursts within an open row. 32-bit AXI-4 target port supporting INCR bursts. #MEMORY MASTER RAM DDR3 FREE#
To be open-source, free to use, free to modify.To be substantially smaller (using fewer FPGA LUTs) than commercial DDR3 cores (such as Xilinx MIG).Support an AXI-4 target port with burst capabilities.Achieve high performance (for the clock speed) sequential read/write performance.Support multiple FPGA vendors/toolchains.Run at a reduced DDR clock speed (However, it is possible to turn the DDR3 DLL off (in most DRAM parts) and run at frequencies <= 125MHz.ĭLL-off mode (which this memory controller utilises) is listed as an optional feature for DDR3 parts to implement, however it seems that the popular DDR3 parts do implement it (and testing proves that it works well)! Design Targets In normal operating mode (DLL-on mode), DDR3 has a minimum clock frequency (300MHz+). This can make sense for some FPGA projects where the fabric speed is limiting factor in the design, rather than the external DDR memory interface speed, and where typically an SDR DRAM could have been used but wasn't (for reasons of availability, capacity, cost per bit).ĭDR3 has a very high signalling rate, and in order for this to work reliably, it has added complexity such as The idea with this project is to run DDR3 at a much slower clock frequency than the maximum supported by the DDR part, reducing the complexity required in the DDR3 controller by giving the bus interface much more margin and tolerance.
#MEMORY MASTER RAM DDR3 SERIES#
It currently supports Xilinx 7 series (Artix, Kintex) and Lattice ECP5 FPGAs, but other FPGA specific DFI compatible PHYs might be added later. This IP is a compact DDR3 memory controller in Verilog aimed at FPGA projects where the bandwidth required from the memory is lower than DDR3 DRAMs can provide, and where simplicity and LUT usage are more important than maximising the DDR performance.
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